AI Cascade Bottleneck -- Part V
CPO going from 0-100 soon, maybe?
All financial data as of close 2026-05-11 unless noted. Quarter-end dates per the latest 10-Q/10-K/20-F filings.
As always, none of this is investment advice, and it’s not trading advice. I am a 38-year-old professional with a love for equity analysis and investing. This documents my thoughts and my research, nothing else. In addition, as with all my work here, it contains a lot of AI work. I do all the research myself using Unusual Whales, Benzinga, and Massive.com data. I formulate my thoughts. Go through them. And then I have Claude put everything together, before I look it over one final time.
This is where it starts to get interesting. Nobody wants to jump into shares after they have blown up 10x in a year. From this part forward, we are looking into what could be coming next. As always, tech stuff upfront, financials towards the end.
TLDR: We are in the middle of the photonics bottleneck right now, CPO should be the next step.
Part V — The Interconnect Layer: Optical Networking, Co-Packaged Optics, and the InP Bottleneck
A note before this Part begins
First, the interconnect layer is the segment of the AI cascade where vendor-promotional material is most heavily mixed with credentialed third-party research, and where market-size projections have the widest fan of disagreement of any layer covered in this article. Co-Packaged Optics (CPO) penetration forecasts from TrendForce and equipment suppliers extend to 2030 and 2032; the deepest projections — particularly the 2032 numbers — rest on vendor-promotional source material that the data-capture process flagged as unreliable. Wherever a 2030+ TAM number appears in this Part, the confidence level is disclosed and the methodology weakness is stated. The reader should treat all CPO penetration numbers beyond 2028 as scenarios, not forecasts.
Second, the cleanest pure-play exposure to the most concentrated bottlenecks in this layer — the optical engine assemblers, the InP epitaxy foundries, the CPO connector and thermal-module sole-source suppliers — sits on Asian exchanges (Shenzhen, Taipei TWSE, Taipei TPEX, Tokyo) that US retail brokerage accounts cannot directly access. Sub-section V-7 documents which Asian names matter and why; investors should understand that the US-listed expressions of this thesis are second-best by design, not by accident.
Third, the optical equipment sector has produced more permanent capital impairments per cycle than any other layer of this stack. Between 2000 and 2010 the names that defined “telecom optical” — Nortel Networks, JDS Uniphase, Bookham, Avanex, OpNext, NetLogic, Acacia (acquired Cisco at distressed multiples), Inphi (acquired Marvell), Finisar (merged into II-VI), Oclaro, EMCORE — either went bankrupt, were acquired at a fraction of their peak market capitalization, or compounded value at rates worse than treasury bills for 15-year periods. The survivor names that dominate today’s AI optical thesis — Lumentum, Coherent, Ciena, Fabrinet, Applied Optoelectronics — are the rump of an industry whose median outcome was severe equity destruction. An investor who buys the 2026 optical thesis without understanding that history is buying selectively into one of the most cyclically violent equity universes in semiconductor history. Section V-2 references this history explicitly; Section V-6 carries the same warning into the company-specific deep dives.
This Part is structured in seven sub-sections. V-1 establishes the physics of why copper-based electrical interconnects fail at 200 Gb/s per lane and why optical wins. V-2 walks through the pluggable transceiver architecture and the 400G → 800G → 1.6T evolution. V-3 covers the InP laser bottleneck that is the central supply-chain pinch of the 2025-2027 cycle. V-4 covers the architectural shift to Co-Packaged Optics. V-5 covers silicon photonics and the foundry layer. V-6 provides company-by-company deep dives on the twelve US-listed names with material optical exposure. V-7 covers the Asian-listed names that US retail cannot access.
V-1. Why copper fails and optical wins
The signal integrity arithmetic at 200 Gb/s per lane
Every high-speed digital interconnect — between a CPU and DRAM, between a GPU and its host, between a switch ASIC and the front-panel port — operates on a signaling lane. A lane is one differential pair of wires (two conductors carrying complementary signals) running at some bit rate. The aggregate throughput of a port equals the per-lane bit rate multiplied by the number of lanes in parallel. Modern AI fabric speeds — 400 Gb/s, 800 Gb/s, 1.6 Tb/s per port — are built from groupings of 50, 100, 200, and (in roadmap) 400 Gb/s lanes.
The physics is hostile. A copper trace on a printed circuit board (PCB), at the frequencies required to carry 200 Gb/s on a single differential pair using four-level pulse amplitude modulation (PAM-4 — encoding two bits per symbol at 100 Gbaud), suffers from three forms of degradation that compound non-linearly with frequency. The first is dielectric loss: the insulating material between conductor and ground plane absorbs energy from the propagating electromagnetic wave, and the absorption coefficient rises roughly linearly with frequency. The second is skin-effect loss: at gigahertz frequencies, current flows only in a thin outer layer of the conductor, raising effective resistance. The third is intersymbol interference: each transmitted symbol “smears” into adjacent symbols because the channel’s frequency response is non-flat, and an equalizer must reconstruct the original sequence.
Together, these effects mean that the bandwidth-distance product of a copper channel is roughly fixed. Doubling the bit rate roughly halves the maximum usable channel length. At 100 Gb/s per lane (the building block of 400G Ethernet), copper channels of 20-30 cm are practical on standard FR-4 PCB material with one or two retimer/equalizer chips along the path. At 200 Gb/s per lane (the building block of 1.6T Ethernet), the practical channel length drops to roughly 7-10 cm with aggressive equalization — and falls below 5 cm without it.
The Open Compute Project (OCP) has published reference designs for 1.6T switches that explicitly call out this constraint: the path from the switch ASIC’s serializer/deserializer (SerDes) circuit to the front-panel optical module faceplate cannot be made short enough on a conventional PCB layout to preserve signal integrity. The system either requires a retimer chip in the middle of the path — adding power, latency, and cost — or requires a different physical interconnect medium beyond a certain distance threshold. That medium is optical fiber.
The optical link budget
An optical link converts electrical pulses into modulated light, transmits the light through a glass or polymer waveguide (typically a single-mode silica fiber for data center distances), and converts the light back to electrical pulses at the receiver. The conversion is lossy at both ends, but the fiber itself is extraordinarily low-loss: single-mode fiber attenuates light at approximately 0.2 dB per kilometer at the 1550 nm wavelength used in long-haul telecom, and approximately 0.4 dB per kilometer at the 1310 nm wavelength favored in datacenter applications. By comparison, a copper PCB trace at 100 Gbaud loses on the order of 1 dB per centimeter — five orders of magnitude worse on a per-length basis.
The “optical link budget” is the engineer’s bookkeeping for power across the link. The transmitter emits optical power at some level — typically 0 to +5 dBm (1 to 3 mW) for short-reach datacenter optics, higher for longer-reach links. Losses along the path subtract from this number: fiber attenuation, connector losses (typically 0.3 dB per mated pair), splice losses, and any insertion losses from multiplexers or other passive optics. The receiver requires a minimum input power to operate at the required bit error rate — typically -10 to -15 dBm for direct-detect receivers at 100 Gbaud. The difference between transmitter output, summed losses, and required receiver input is the link margin, which must be positive for the link to function reliably under worst-case conditions (temperature extremes, component aging, manufacturing variation).
At each speed grade, the link budget tightens. Higher bit rates require more photons per bit to achieve the same bit error rate, which means higher launched power or shorter reach. The progression from 400G to 800G to 1.6T per port has not changed the underlying physics — but it has changed the modulation, the laser power, the receiver sensitivity, and the digital signal processing required to keep the budget positive. Each step has consumed more power per gigabit per second moved, even as the per-bit cost has continued to decline.
Why the transition keeps accelerating
Three forces drive the data center interconnect transition from copper toward optical. The first is bandwidth: AI training and inference workloads demand bidirectional bandwidth between accelerators that scales with model size and with cluster size. The second is distance: rack-scale AI deployments (NVIDIA GB200 NVL72 racks, AMD Instinct racks, custom hyperscaler designs) are pushing the boundary of what copper can deliver even inside a single rack, and inter-rack fabrics for large training clusters routinely require runs of tens of meters that copper cannot serve at any speed. The third is power. At 1.6T port speeds, the dominant power consumer in a network switch is no longer the switch ASIC itself — it is the SerDes and equalization circuitry needed to drive copper between the ASIC and the faceplate. Industry-cited numbers place this at roughly 15-16 watts per 800G port for the current generation of pluggable optics, much of which is the electrical drive rather than the optical conversion proper. At 1.6T the number grows worse.
The investor takeaway is structural rather than tactical. The transition from copper to optical at progressively shorter distances is not a question of whether, but when. Copper has dominated below the rack level for thirty years; below the chip-to-chip level it remains uncontested because of cost and density. But at every speed transition — 100G to 400G to 800G to 1.6T — the threshold distance at which optical becomes mandatory has shrunk. Co-Packaged Optics, discussed in Section V-4, push that threshold all the way to the ASIC package itself.
Acronyms used in this section
• Gb/s, Tb/s — Gigabits per second, terabits per second.
• Gbaud — Gigabaud, gigasymbols per second; the symbol rate (not bit rate) of a channel.
• PAM-4 — Four-level Pulse Amplitude Modulation; encodes two bits per symbol.
• PCB — Printed Circuit Board.
• SerDes — Serializer/Deserializer; the circuit that converts parallel data into a high-speed serial stream.
• OCP — Open Compute Project.
• dB, dBm — Decibels (ratio in log scale), decibel-milliwatts (absolute power in log scale).
• nm — Nanometers; wavelength unit.
• FR-4 — Standard PCB substrate material.
V-2. Pluggable transceivers
What the module actually contains
A pluggable transceiver is a self-contained electro-optical conversion module that plugs into a front-panel port on a network switch. The mechanical form factor is standardized — QSFP28 for 100G, QSFP-DD or OSFP for 400G and 800G, OSFP800 and CPO-MSA-defined variants emerging for 1.6T — and the electrical and optical interfaces are defined by Multi-Source Agreements (MSAs) that ensure interoperability between modules from different vendors.
Inside the module, four functional blocks do the work. First, the electrical interface: a connector edge that mates with the switch motherboard and carries the high-speed electrical signal (typically PAM-4 at 50, 100, or 200 Gb/s per lane) plus management, power, and identification signals. Second, the digital signal processor (DSP) — also called a “retimer” — which receives the electrical signal from the host, recovers the clock, retimes the data, equalizes for channel impairments, and re-encodes the data for transmission to the laser driver. The DSP is the single largest power consumer in a modern pluggable, typically drawing 6-9 watts at 800G. Marvell (post-Inphi acquisition), Broadcom, and Credo Technology are the dominant DSP suppliers. Third, the laser driver and modulator (often integrated with the DSP and laser chips on a single optical sub-assembly), which converts the electrical signal into a modulated optical signal at the appropriate wavelength. Fourth, the optical sub-assembly itself — laser, modulator, photodetector, fiber alignment optics — which performs the electro-optical conversion. This is where the InP-based components, discussed in Section V-3, reside.
A typical 800G module shipping in 2025-2026 contains 8 lanes at 100 Gb/s per lane, or 4 lanes at 200 Gb/s per lane. Each lane requires one transmit laser and one receive photodetector. At the 8x100G variant — the bulk of installed base — that is eight EML (Electro-absorption Modulated Laser) chips per module, plus eight photodiodes (typically PIN or APD detectors) and a sophisticated alignment package to couple light into and out of the fibers.
The 400G to 800G to 1.6T progression
Optical transceiver speed roadmap 400G to 3.2T.
400G optics began ramping in volume in 2019-2020, driven initially by hyperscale data center spine networks (Google, Meta, Microsoft, AWS) and quickly extending to the AI training fabric layer. The dominant 400G implementations used either 8x50G PAM-4 or 4x100G PAM-4 lane structures. Power consumption settled in the 7-10W range per module after early-generation optimization.
800G ramped from 2022, and by 2024-2025 represented the dominant new build-out speed grade in AI data center networks. The 800G generation introduced 100 Gb/s per lane PAM-4 as the workhorse lane rate, with both 8x100G and 4x200G variants in production. Power consumption per 800G module stabilized at roughly 15-16 watts — twice the bandwidth of 400G at roughly twice the power, a constant-energy-per-bit outcome that masks the underlying difficulty of getting 100 Gb/s per lane working at scale.
1.6T is the current ramp. The first 1.6T silicon shipped in late 2024 (Broadcom Tomahawk 5, Marvell switch silicon roadmap, NVIDIA Spectrum-X/Quantum-X products), and the first 1.6T pluggable modules began limited deployment in 2025. Most 1.6T modules use 8x200G PAM-4 — eight lanes each carrying 200 Gb/s using PAM-4 modulation at 100 Gbaud per lane. The optics complexity at 200G per lane is materially harder than at 100G: signal integrity margins are tighter, equalization is more aggressive, and the optical components themselves — especially the EML laser — must operate at higher bandwidth with tighter wavelength stability. Power per module at 1.6T is currently in the 20-25W range, with hyperscale customers pushing for lower power as a procurement criterion.
The cluster math is where this becomes investor-relevant. A modern AI training cluster of 100,000 GPUs requires on the order of 200,000 to 400,000 optical transceiver ports across the fabric layers (top-of-rack switches, leaf switches, spine switches, and the GPU-direct connections themselves in some architectures). At 800G with 15W per module, the total transceiver power draw is on the order of 3-6 megawatts — for a 100MW-scale cluster, this is 3-6% of total facility power, just for the optics. At 1.6T with 20-25W per module, the percentage rises. Multiply across the dozens of 100,000+ GPU clusters being deployed through 2026-2028, and the aggregate transceiver demand becomes a major bottleneck input.
The faceplate connector and the density problem
Transceiver density is constrained by the front-panel area of a switch chassis. A typical 1U switch chassis can accommodate 32 to 36 ports on its front panel. At 800G per port, that is 25-29 Tb/s of full-duplex bandwidth from a single 1U switch. At 1.6T per port, 51-58 Tb/s. This density is set by mechanical constraints — connector size, cooling airflow paths, and the physical room for the module body to extend into the chassis.
Pushing higher density at the faceplate without changing the module form factor is essentially impossible; the connector standards lock the dimensions. What does change with each generation is power and thermal: more bandwidth per port at a fixed mechanical envelope means more watts per cubic centimeter of module, which means more aggressive cooling design and tighter operating temperature margins. The OSFP and OSFP800 standards include integral heatsink and airflow design specifications precisely because module thermal management has become a system-level design constraint, not a vendor-level optimization.
What pluggable transceivers actually cost
The 800G transceiver price has compressed materially since 2022. List prices for 800G DR8 (Datacenter Reach, 8 lanes) modules in 2025 ranged from $700 to $1,200 depending on volume, supplier, and reach variant. 800G modules with longer reach (FR8, LR8, ZR variants) command premiums. The cost structure inside the module is roughly: optical sub-assembly (lasers, modulator, detectors, fiber alignment) at 40-50% of bill of materials, DSP at 15-20%, mechanical and connector at 15-20%, balance in driver electronics, microcontroller, firmware, and assembly labor.
Hyperscale procurement contracts push these prices well below list, especially for high-volume single-mode variants. The aggregate optical transceiver TAM has been variously estimated at $12-18 billion in 2025, projected to $25-40 billion by 2028 (multiple syndicated research outlets; LightCounting and Cignal AI being the most-cited specialist firms). The methodology spread is wide enough that the high and low bounds differ by roughly 2x. For investor sizing purposes, treat the 2028 transceiver TAM as $25-35 billion with medium confidence and a meaningful CPO-substitution risk at the upper end (Section V-4 disassembles that).
The historical mortality of optical equipment names
This is the section that survivor bias most strongly distorts. The optical equipment industry has a history that an investor approaching 2026 valuations should understand before committing capital.
The 2000-2002 telecom optical crash destroyed an estimated 90%+ of the equity capitalization of the public optical-component sector. JDS Uniphase, the dominant optical-component name of the dot-com era, peaked at a market capitalization of roughly $200 billion in 2000; by 2002 the same business traded at less than $5 billion, and the renamed entity (JDSU, then Lumentum after a 2015 spinoff) never recovered to within 50% of the 2000 peak on an inflation-adjusted basis through 2024. Nortel Networks, the optical systems leader, filed for bankruptcy in 2009. Bookham, Avanex, OpNext — all consolidated into Oclaro, which itself was acquired by Lumentum in 2018 at a price that represented a small fraction of the combined predecessor companies’ peak valuations. EMCORE shrunk into a microcap. Finisar merged with II-VI in 2019 at multiples that were attractive only because Finisar had failed to grow into the expectations of its 2014-2017 peak.
The names that survived to dominate today’s AI optical thesis — Lumentum, Coherent (formerly II-VI), Fabrinet, Ciena — did so by surviving rather than by winning. The pattern of permanent capital impairment across the broader sector is not a 2000 artifact: Acacia Communications was acquired by Cisco in 2021 after a multi-year decline from its 2016 IPO peak. Inphi was acquired by Marvell in 2021 at a premium but at a multiple that reflected slowing growth into a maturing 400G market. Even the consolidation-survivors traded sideways or worse from 2015 through 2022 before the AI cascade started lifting them.
The 2025-2026 rally has been violent. Lumentum has run from a 52-week low of $63.98 to $903.80 — a 14x move in twelve months. Coherent from $69.87 to $335.26, nearly 5x. Fabrinet from $208 to $621, 3x. Applied Optoelectronics from $14.76 to $148.94, a 10x rally that is one of the largest single-name moves in the entire AI cascade. Aehr Test Systems from $8.43 to $97.23, a 10x+ rally on a small float that has produced extreme volatility. These are not normal optical-sector returns. They reflect a thesis-specific reflation overlaid on a sector that has been priced for cyclical destruction for two decades. The thesis is real. The valuations now embed expectations that, if a single year of disappointment intervenes, are positioned to mean-revert violently. Section V-6 will revisit this for each name.
Acronyms used in this section
• QSFP, QSFP28, QSFP-DD, OSFP — Quad Small Form-factor Pluggable transceiver mechanical standards.
• MSA — Multi-Source Agreement; the industry standards documents that define transceiver form factors and interfaces.
• DSP — Digital Signal Processor; the chip inside a transceiver that retimes and equalizes the electrical signal.
• EML — Electro-absorption Modulated Laser; the dominant 800G/1.6T short-reach laser type.
• PIN, APD — Positive-Intrinsic-Negative diode, Avalanche Photodiode; two types of receive photodetector.
• DR8, FR8, LR8, ZR — Reach variants of pluggable optics (DR = Data center Reach ~500m, FR = Far Reach ~2km, LR = Long Reach ~10km, ZR = ultra-long-reach with coherent optics).
V-3. The InP laser bottleneck (~2,500 words)
Why silicon cannot make lasers
The most direct way to explain the InP bottleneck is to start with what silicon cannot do. Silicon is the workhorse semiconductor material of digital logic because it can be grown in defect-free crystalline ingots at industrial scale, fabricated into transistors with extraordinarily small feature sizes, and supplied at low cost. But silicon has a property that disqualifies it from being a practical light emitter: it has an indirect bandgap.
The bandgap of a semiconductor is the minimum energy required to lift an electron from the valence band — where it is bonded to a lattice atom — into the conduction band, where it is free to move and conduct current. When an electron in the conduction band falls back into the valence band, it releases energy equal to the bandgap. In a direct bandgap material, that energy is released primarily as a photon — a particle of light. In an indirect bandgap material, the energy is released primarily as a phonon — a vibration of the crystal lattice, which is to say, as heat. Silicon is indirect: when silicon electrons recombine, the energy mostly leaves as heat, not light. The fraction that leaves as light is so small that silicon cannot serve as a useful laser medium at any reasonable operating point.
This is a fundamental physics constraint, not an engineering problem awaiting a clever solution. SPIE, the international professional society for optics and photonics, has covered the long history of failed attempts to make silicon a viable laser medium (SPIE, “Silicon Lasers: The Final Frontier,” July/August 2020). The research community has produced silicon-based light emitters using various tricks — porous silicon, Raman lasing, nanowire structures, strained germanium-on-silicon — but none have achieved the combination of efficiency, modulation speed, output power, and manufacturing repeatability required for a commercial product at gigabit data rates. Every commercially deployed laser in every commercially deployed optical transceiver, as of 2026, uses a direct-bandgap compound semiconductor — most commonly indium phosphide (InP), with gallium arsenide (GaAs) used for some shorter-wavelength applications.
Indium phosphide has a direct bandgap of approximately 1.35 electron-volts, corresponding to a photon wavelength of approximately 920 nm. Through alloying with gallium and arsenic to make ternary or quaternary compounds (InGaAs, InGaAsP, InGaAlAs), the effective bandgap can be tuned to produce light at 1310 nm and 1550 nm — the two wavelengths that dominate datacenter and telecom fiber optic communications, respectively. The 1310 nm window corresponds to the zero-dispersion wavelength of standard single-mode fiber; the 1550 nm window corresponds to the minimum-attenuation wavelength.
The investor consequence is this: every laser that goes into a fiber-optic transceiver, regardless of speed grade, must be fabricated from a compound semiconductor material that requires an entirely separate fabrication ecosystem from the silicon CMOS fabs that produce GPUs, CPUs, memory, and most logic. The InP fab ecosystem is small, specialized, and has been historically capital-constrained because it served the modest demand of telecom optics. The AI cascade has dropped a demand step-change onto an industry that was not built for it.
EML, DFB, and CW: three flavors of laser, used differently
Inside the catch-all term “InP laser” sit three distinct device categories, each serving a different role in a transceiver or CPO module.
The Distributed Feedback (DFB) laser is the workhorse continuous-wave (CW) laser. It produces light at a fixed wavelength determined by a periodic grating fabricated into the laser cavity. DFB lasers are stable, narrow-linewidth, and relatively low power — typical output a few milliwatts to tens of milliwatts. They are used in two roles in modern optics: as a CW light source whose output is modulated externally by a separate modulator, and as a direct-modulation source where the drive current itself carries the data signal. Direct-modulation DFB lasers are the standard for older and lower-speed transceivers (100G, some 400G) where simplicity and cost matter more than performance.
The Electro-absorption Modulated Laser (EML) integrates a DFB section with an Electro-absorption Modulator (EAM) section on the same InP chip. The DFB section produces continuous-wave light; the EAM section, which sits adjacent to the DFB on the same substrate, absorbs or transmits that light depending on the voltage applied to it. Modulation speeds reach 50-60 GHz, which is what enables 100 Gb/s and 200 Gb/s per lane PAM-4 operation. EML is the dominant laser type in 800G and 1.6T short-reach datacenter optics. It is also the device most directly constrained by the current InP capacity shortage, because every 800G module contains 4 to 8 EMLs, depending on the lane structure.
The pure Continuous-Wave (CW) DFB laser, with no integrated modulator, is the device used in two emerging applications: as the seed source for silicon photonics modulators (where modulation happens off-chip on a silicon photonic integrated circuit), and as the External Laser Source (ELS) for Co-Packaged Optics (Section V-4). The CW DFB market has historically been small because pluggable transceivers used integrated EMLs; the CPO transition shifts demand toward CW DFBs in higher power variants. This is part of why CPO is not purely dilutive to laser demand, even as it reduces lasers per gigabit shipped — the device mix shifts, and the higher-power CW DFB has a different cost basis from the EML it partially replaces.
A third device class deserves mention: the tunable laser, used in coherent optics for long-reach (>10 km) applications and in some emerging WDM (Wavelength Division Multiplexing) architectures. Tunable lasers — typically Distributed Bragg Reflector (DBR) or external-cavity designs — can produce light across a range of wavelengths under electronic control. They are more expensive per unit and lower-volume than DFBs or EMLs, and the AI cascade has only marginally affected the tunable laser market because most AI datacenter optics use direct detection rather than coherent detection at short reach.
Wavelength Division Multiplexing
Wavelength Division Multiplexing (WDM) is the technique of sending multiple optical signals at different wavelengths down the same fiber. A coarse WDM (CWDM) system uses wavelengths separated by 20 nm in the 1270-1610 nm window — typically 4 to 8 channels. A dense WDM (DWDM) system uses wavelengths separated by 0.4 to 0.8 nm — up to 80 or 96 channels in commercial deployments — and is more typical of long-haul telecom. The CWDM4 and CWDM8 variants are common in datacenter optics, with each transmitter using a different wavelength so that four or eight parallel data streams can share one fiber.
Wavelength multiplexing matters for the laser-demand math in two ways. First, every CWDM channel requires its own laser tuned to its own wavelength — so the per-module laser count is set by the number of channels, not by the bit rate per se. A 400G 8x50G transceiver has 8 lasers; a 400G 4x100G CWDM4 transceiver has 4 lasers. Second, the wavelength multiplexer and demultiplexer optics add insertion loss to the link budget (typically 2-4 dB per pair), which constrains the reach of WDM modules and pushes some applications toward parallel single-mode fiber architectures that avoid the multiplexer entirely.
InP fab capacity globally
The InP fab ecosystem is concentrated. The largest captive-plus-merchant InP fabs in the world, as of 2025, are operated by Lumentum, Coherent (formerly II-VI), Sumitomo Electric (Japan), Mitsubishi Electric (Japan), and NTT Electronics (Japan, primarily captive). Lumentum’s InP capacity is split between the Bloomfield, Connecticut (formerly Oclaro) and San Jose, California facilities; Coherent’s between Sherman, Texas and additional sites. Capacity in 2025 is measured in tens of thousands of wafer-starts per year — globally, a few hundred thousand 3-inch and 4-inch InP wafers per year, which is roughly two orders of magnitude smaller than the silicon CMOS wafer industry.
The capacity shortage has been quantified by TrendForce, the Taiwan-based research firm. Their December 2025 note projected an industry shortfall of approximately 36% in EML laser supply versus demand through 2027 (TrendForce, December 2025). This is the figure that gets cited most often. The methodology underlying the 36% number is not fully published by TrendForce — it is a subscription research note — but the directional shape of the projection has been corroborated by multiple sell-side optics specialists (Susquehanna, Needham, Rosenblatt) and by management commentary from both Lumentum and Coherent in late-2025 and early-2026 earnings calls. The 36% figure should be treated as the central estimate from a single specialist research firm with corroboration from secondary sources; the range plausible from alternate methodologies is roughly 20-50% shortfall.
The capacity expansion path is constrained by three factors. First, InP wafer substrate supply itself — the boules of single-crystal InP from which wafers are sliced — is dominated by a handful of producers (Sumitomo, AXT, Wafer Technology Ltd) and has historically been a supply chain pinch point during prior shortages. Second, InP epitaxy capacity — the metalorganic chemical vapor deposition (MOCVD) growth of the active laser layers on the wafer — requires capital investment with 18-24 month lead times for tool delivery and process qualification. Third, downstream chip-level packaging and burn-in capacity, which is the segment Aehr Test Systems serves, has its own bottleneck dynamics.
The NVIDIA $4 billion investment
In March 2026, NVIDIA disclosed parallel equity investments of approximately $2 billion each in Lumentum and Coherent, totaling roughly $4 billion deployed into the InP laser supplier base. The terms were disclosed in regulatory filings: 2.9 million Lumentum shares purchased at $695.31 per share (= roughly $2.02 billion), and 7.8 million Coherent shares purchased at $256.80 per share (= roughly $2.00 billion). optics.org coverage of the deal describes the strategic rationale as securing future laser supply for both pluggable transceivers and the emerging CPO architecture.
The structural read on these investments is more complicated than vendor-promotional summaries suggest, and an investor should be precise about what the public filings did and did not say.
What the filings said: NVIDIA acquired equity stakes in both companies at specified share counts and prices. The investments are minority positions — well below 10% of either company’s shares outstanding. The press releases describe the investments as supporting AI infrastructure scaling and laser supply for current pluggable and future CPO product lines.
What the filings did not say: there is no public disclosure of exclusivity terms in either investment agreement. Neither Lumentum nor Coherent has filed an 8-K or S-1-equivalent supplement disclosing that any portion of their forward capacity is exclusively reserved for NVIDIA. The press releases and proxy statements that have been made public describe commercial supply commitments and equity ownership but not exclusivity. Sell-side commentary has occasionally interpreted the investments as creating de facto exclusivity through priority allocation; the actual contractual structure is opaque from public sources alone.
The investor consequence: NVIDIA has materially strengthened its allocation priority at the two largest Western InP fabs, but the laser supply going to AMD, Broadcom-Google TPU, Amazon Trainium, and the merchant pluggable market is not contractually displaced. The $4 billion is a positioning move, not a lockout. Other accelerator customers can still buy from Lumentum and Coherent at the prevailing market price; what they have lost is the option to negotiate first allocation priority at the next capacity ramp. This is a meaningful but bounded strategic effect.
A second-order point: the equity investments also align NVIDIA’s interests with the long-term equity value of LITE and COHR, which incentivizes NVIDIA to continue routing CPO-related capacity buildouts through these suppliers rather than vertically integrating laser fabrication itself. The political-economy of the supply chain is now structurally tighter than it was twelve months ago.
Bull case: laser demand keeps growing even as CPO transitions
The simplistic bear case on InP lasers in a CPO world is “CPO uses fewer lasers per gigabit, so the laser demand falls.” This is wrong on the absolute numbers, and the math is worth doing carefully.
Take a baseline AI fabric in 2025 shipping 800G pluggable optics. Each module has eight lanes, eight EMLs, eight photodetectors. Across an industry shipping 10 million 800G ports in 2025, that is 80 million EML lasers consumed.
Now project forward to 2028. AI fabric port volume could plausibly grow 4-6x — driven by GPU cluster scale, increased per-GPU port count, and a transition to 1.6T as the dominant new build speed. Take 5x as a midpoint = 50 million 1.6T-equivalent ports. CPO penetration on those ports might reach 15-20% by 2028 (slower than the 35% by 2030 implied by TrendForce, but those numbers carry the methodology caveats discussed in V-4). Call it 18% midpoint = 9 million CPO ports and 41 million pluggable ports.
Pluggable 1.6T optics typically use 8 lanes with 8 EMLs each → 41M × 8 = 328 million EMLs in the pluggable market alone in 2028. CPO modules use roughly 0.25 lasers per lane (per NVIDIA’s published architectural description, the ELS module contains 8 lasers feeding 32 transmit lanes) → 9M × 32 lanes × 0.25 = 72 million CW DFB lasers in CPO. Total InP laser-die demand in 2028 ≈ 400 million, against ~80 million in 2025 — a 5x increase, not a decrease.
The math is sensitive to assumptions, particularly CPO penetration and per-module laser count (which depends on lane structure and on whether next-gen CPO modules consolidate further). But the central qualitative point holds: AI traffic growth outpaces the per-Gbps laser efficiency gain from CPO by a wide margin through 2028. Both the EML and the CW DFB segments grow in absolute terms even as their relative weights shift.
The lower-confidence longer-horizon view extends to 2030. If CPO penetration reaches 35% by 2030 (TrendForce central estimate, methodology caveats per V-4) and AI fabric port volume continues to grow at 30-50% CAGR, the laser-die demand reaches 800-1200 million units per year. This is a 10-15x increase versus 2025. The merchant InP capacity to serve this demand does not currently exist. Either capacity ramps to meet it (which is the bull case for LITE and COHR), or pricing rations supply (which is the same bull case in a different form), or the demand falls short (which is the bear case on the whole optical thesis).
Counter-case: indium concentration in China, substitution options
The bear arguments on the laser supply chain are concentrated on raw-material risk and on substitution scenarios.
Indium itself — the chemical element, atomic number 49 — is supplied dominantly by China. Approximately 60% of global indium production comes from Chinese mines, with primary sources in Yunnan, Inner Mongolia, and Guangxi. Indium is a byproduct of zinc ore processing, and global production is roughly 800-1000 tonnes per year. The amount of indium used per InP laser die is microscopic — a fraction of a milligram — but aggregate demand from photovoltaic, display (transparent conductive oxide), and semiconductor markets places ongoing pressure on availability. China imposed indium export quotas in 2023-2024 alongside its broader rare-earth and critical-minerals export controls, and the U.S. has identified indium as a critical mineral subject to Defense Production Act considerations.
The supply chain risk is real but bounded. Indium recycling from end-of-life display panels has been expanding and could supply 30-40% of demand over the medium term. Alternative laser materials — particularly gallium nitride (GaN) for some wavelength bands and aluminum gallium indium arsenide (AlGaInAs) for some 1310 nm applications — provide partial substitution paths but cannot displace InP for the 1550 nm long-haul applications or for the high-bandwidth EMLs that 1.6T optics require.
The second substitution-path argument is more nuanced: silicon photonics with external InP laser sources, discussed in Section V-5. Silicon photonics displaces the InP-fabricated modulator and waveguide structures with silicon-fabricated equivalents, but still requires an InP laser to provide the light. So the silicon photonics transition reduces the InP-fabricated bill of materials but does not eliminate it; the InP laser remains the unsubstitutable element. The bull case on Lumentum and Coherent is essentially that they own the unsubstitutable layer.
Acronyms used in this section
• InP — Indium Phosphide; the dominant direct-bandgap compound semiconductor for telecom-wavelength lasers.
• GaAs — Gallium Arsenide; alternative direct-bandgap material for shorter wavelengths.
• DFB — Distributed Feedback laser; a single-wavelength CW laser type.
• EML — Electro-absorption Modulated Laser; integrated DFB plus modulator.
• EAM — Electro-absorption Modulator.
• CW — Continuous Wave; describes a laser operating at constant output without modulation.
• DBR — Distributed Bragg Reflector laser; a tunable laser type.
• WDM, CWDM, DWDM — Wavelength Division Multiplexing; Coarse and Dense variants.
• MOCVD — Metalorganic Chemical Vapor Deposition; the epitaxy process used to grow laser active layers.
• GaN — Gallium Nitride; alternative compound semiconductor.
V-4. Co-packaged optics (CPO) (~2,500 words)
Pluggable vs co-packaged optics architecture. Shrinking the electrical link from 30cm to 1cm. Source: NVIDIA Developer Blog.
The architectural shift
Co-Packaged Optics is not an incremental optimization of the pluggable transceiver. It is a complete restructuring of where the electro-optical conversion happens relative to the compute silicon. The pluggable architecture places the optics at the front-panel faceplate of the switch chassis — typically 30 to 50 centimeters of high-speed electrical channel away from the switch ASIC. The CPO architecture places the optics in the same package as the switch ASIC, on a shared substrate, with electrical channel lengths measured in millimeters rather than centimeters.
The motivation is power, and the math is concrete. A pluggable 800G transceiver consumes approximately 15-16 watts at the module level, of which the dominant fraction is the SerDes and equalization required to drive the 30+ cm of host PCB trace between the ASIC and the front panel. Broadcom’s “Bailly” CPO switch — the Tomahawk 5 silicon paired with co-packaged optical engines — consumes approximately 5.4 watts per 800G port, a roughly 65% reduction or a 3.5x efficiency improvement (NVIDIA Developer Blog, SENKO). For a 1.6T port, the per-port savings is even larger in absolute watts. Scaled across a 100,000-GPU AI training cluster with hundreds of thousands of optical ports, the aggregate power savings is in the multiple-megawatts range.
The architectural diagram tells the story compactly. The pluggable signal path is: ASIC → on-die SerDes → host PCB trace (~30 cm) → DSP retimer chip → faceplate connector → pluggable module electrical interface → module DSP → laser driver → laser → fiber. The CPO signal path is: ASIC → on-die SerDes → substrate trace (~1 cm) → optical engine (containing modulator, driver, photodetector) → fiber array. The DSP retimer drops out. The host PCB trace shrinks by an order of magnitude. The SerDes can be lower-power because it drives a shorter, lower-loss channel.
This is a re-architecture of the electrical signal path, not a re-architecture of the optics. The lasers, modulators, and photodetectors still exist; they have just moved from the faceplate to the substrate.
The External Laser Source
External Laser Source modules — 0.25 lasers per lane in CPO vs 1 per lane in pluggables. Source: NVIDIA disclosure.
In a pluggable transceiver, each lane has its own laser inside the module. In a CPO module, the laser is external to the optical engine and sits in a separate package called an External Laser Source (ELS). The reason for this separation is thermal: lasers are sensitive to temperature, requiring stable operating conditions to maintain wavelength and output power. The optical engine, sitting next to the switch ASIC, runs at the elevated temperatures dictated by ASIC power dissipation; separating the lasers preserves their operating environment.
NVIDIA has disclosed the architectural details (NVIDIA Developer Blog on CPO Industry Collaboration). Each ELS module contains 8 high-power continuous-wave DFB lasers and feeds 32 transmit lanes — meaning the ratio is 0.25 lasers per lane in CPO architecture, versus 1 laser per lane in the pluggable architecture. NVIDIA’s own description states that CPO “reduces the total number of lasers in the data center by a factor of four compared to legacy designs.”
The single CW DFB feeds multiple lanes through WDM. The light from one laser is split into multiple optical paths; each path is independently modulated by a silicon photonic modulator (Section V-5) before being multiplexed onto the outgoing fiber. The architectural saving in lasers comes at the cost of more complex silicon photonic modulator structures and tighter wavelength engineering — the lasers must operate at precisely-controlled wavelengths matched to the modulator’s resonant or absorption characteristics.
The CW DFB lasers used in ELS modules are not the same product as the EMLs used in pluggable transceivers. They are higher-power (typically 100-300 mW versus 5-50 mW for an EML’s DFB section), CW-only (no integrated modulator), and held to tighter wavelength specifications. The InP fab capacity required to produce these devices overlaps significantly with EML production but is not identical — the active layer designs differ, and high-power CW devices have their own yield and reliability considerations.
The counterintuitive supply chain math
CPO power math: per-port and 100k-GPU cluster scale savings. Sources: NVIDIA, SENKO.
Here is the central mathematical point that distinguishes the CPO investment thesis from its naive version: CPO reduces lasers per gigabit, but the absolute laser demand grows because optical traffic grows faster than the architecture transition can compensate.
Worked example, calibrated to 2026 baseline figures and TrendForce penetration estimates (with disclosed methodology caveats).
2026 baseline. AI data center fabric demand: roughly 12 million 800G-equivalent ports shipped, dominated by pluggable. Per-port laser count: 8 EMLs per 800G module = 96 million EML laser dies. CPO penetration: 0.5% of modules (per TrendForce 2026 estimate). CPO contribution to laser demand at 0.5% = negligible.
2028 projection. Total port volume grows to 35-50 million ports (3-4x increase, conservative versus 1.6T transition mix). CPO penetration rises to 15-20%. Pluggable share = 80-85% of 35-50M ports = ~30-40M pluggable ports × 8 lasers = 240-320M EMLs. CPO share = 15-20% of 35-50M ports = ~5-10M CPO ports × 8 ELS lasers each (32 lanes per port / 4 lasers per lane equivalent at 32:8 reuse ratio) = 40-80M CW DFBs. Total InP laser-die demand: ~280-400M devices, versus 96M in 2026 — a 3-4x increase, driven entirely by the pluggable side even as CPO contributes meaningfully.
2030 projection. Port volume reaches 80-120M (CAGR continuation). CPO penetration reaches 30-35% (TrendForce central case, methodology caveats below). Pluggable share = 65-70% × 80-120M = 52-84M × 8 = 416-672M EMLs. CPO share = 30-35% × 80-120M = 24-42M × 8 ELS lasers = 192-336M CW DFBs. Total demand = 600M-1B devices. This is roughly a 10x increase from 2026 baseline.
The math has two implications. First, absolute laser demand grows substantially through the CPO transition. The bear case “CPO destroys laser demand” is wrong on the numerical inputs. Second, the mix shifts: EML demand grows at a slower rate than total laser demand, and CW DFB demand grows faster. The capacity expansion plans at Lumentum and Coherent need to address both segments.
The third implication, which the math does not capture but bears mentioning: the laser-die yield, packaging cost, and InP wafer consumption per CW DFB is different from per EML. CW DFBs are typically larger die area (because of higher output power requirements) but simpler structure (no modulator), so the InP wafer consumption per laser-die is not constant across the device mix shift. This makes the wafer-starts capacity planning at LITE and COHR more complex than a simple unit-volume forecast.
Penetration trajectory: scenario range with disclosed methodology weakness
CPO penetration of AI data center optical modules 2026-2032. Vendor projections shown as upper bound.
TrendForce has published CPO penetration estimates extending to 2030: 0.5% of AI data center modules in 2026 → 35% by 2030. A separate source extends to 2032, projecting 50%+ penetration; the data capture process flagged this 2032 source as vendor-promotional in origin (specifically, sourced from optical module vendor marketing material that was not corroborated by independent specialist research). The 2032 number should not be relied upon for investor sizing.
The 2030 number itself rests on assumptions that an investor should examine. CPO penetration depends on: (1) the cost curve of CPO modules versus pluggable equivalents, which depends on silicon photonic foundry capacity and yields; (2) the qualification timeline at hyperscale procurement, where second-source CPO designs from Broadcom, NVIDIA, Marvell, and merchant module vendors mature on different schedules; (3) the system architecture preferences of GPU and accelerator vendors, where NVIDIA’s CPO commitment is strong but AMD’s and the merchant ASIC ecosystem’s is less clear; (4) the cost of failure — CPO modules, by being integrated with the switch ASIC, have repair semantics that differ from pluggable optics, and field experience in 2026-2027 will determine whether the architecture is reliable enough for production at hyperscale.
Honest confidence-weighted view: the directional shape of the TrendForce projection is supported by multiple independent sources. The 0.5% in 2026 is consistent with what individual vendors disclose about their CPO production runs. The 35% by 2030 is the central case of one research firm, with no independent corroboration at that specific number; alternative views from Cignal AI and LightCounting place 2030 CPO penetration in the 15-30% range, suggesting the TrendForce number sits at the high end of credentialed forecasts.
For investor sizing: 2026 CPO is near-zero in revenue terms. 2027-2028 is the early ramp. 2029-2030 is where the meaningful penetration occurs, with reasonable scenarios spanning 15-35%. Treat anything beyond 2030 as a scenario rather than a forecast.
The hyperscale CPO supplier ecosystem
The NVIDIA CPO partner list, per their developer blog and press releases, includes: TSMC (foundry), Browave (optical engines, Taiwan-listed), Coherent (laser supply), Corning (fiber and connectors), Fabrinet (assembly), Foxconn (assembly), Lumentum (laser supply), SENKO (optical connectors, private), SPIL (test, Taiwan-listed), Sumitomo Electric Industries (Japan-listed), and TFC Communication (China-listed). Subsequent sell-side research has extended the list to include Nextronics Engineering Corp (TPEX:8147) as the sole-named provider of both the CPO connector and the cage thermal module in NVIDIA’s CPO stack.
Broadcom’s CPO ecosystem is somewhat different. The Tomahawk 5-Bailly CPO switch uses Broadcom’s own silicon photonic integration combined with InP laser sources from a smaller supplier set. Broadcom has been less transparent about its exact partner list, but the AVGO management has cited “long-standing optical supply chain relationships” in earnings commentary without naming specifics.
The Marvell CPO ecosystem, post-Celestial AI acquisition and post-XConn switching specialist acquisition, brings the vertical integration in-house to a greater degree. Marvell’s stated CPO product strategy is to ship integrated solutions where the SerDes, DSP, silicon photonics, and laser interface are all designed by Marvell (or its acquired entities), with only the laser device itself sourced externally.
Architectural risk: the integration cost
The CPO architecture has a structural disadvantage that sometimes gets glossed over in vendor presentations: the optics are co-packaged with the switch ASIC. If a single optical engine fails, the whole package may need to be replaced — versus a pluggable architecture where a failed module can be swapped at the faceplate in seconds. The cost of failure is therefore higher per event, even if failure rates are lower.
Hyperscale operators have run reliability simulations and field trials on both architectures. The consensus, insofar as one exists, is that CPO can match or exceed pluggable reliability if the optical engine and laser source designs are sufficiently mature — but the early-generation CPO products from 2024-2025 have shown enough field issues that some procurement teams have explicitly delayed CPO adoption to wait for second-generation maturity. This is the “inevitable but not imminent” view that Cignal AI has published consistently (Cignal AI on CPO market timing).
The investor implication is that the CPO ramp is more likely to follow an S-curve with a slow initial decade than a linear progression. The 0.5% → 35% trajectory from 2026 to 2030 assumes the S-curve inflection point lies in 2027-2028, which is consistent with the timing of second-generation products from Broadcom, NVIDIA, and Marvell that are entering qualification in 2026. If the inflection slips by 12-18 months — a plausible outcome given the integration complexity — the 2030 number could be materially lower than 35%.
Acronyms used in this section
• CPO — Co-Packaged Optics.
• ELS — External Laser Source; a separate module containing the lasers that feed a CPO optical engine.
• ASIC — Application-Specific Integrated Circuit; the switch chip in this context.
• PCB — Printed Circuit Board.
• mW — Milliwatts.
• dB — Decibels.
V-5. Silicon photonics (~2,000 words)
What silicon photonics is
Silicon photonics is the fabrication of optical devices — waveguides, modulators, photodetectors, multiplexers, beam splitters, polarization controllers — using silicon-on-insulator (SOI) wafers and the same CMOS-compatible process steps used in conventional logic chip fabrication. The motivating idea is that silicon photonics borrows the cost curve of the silicon semiconductor industry: large-diameter wafers (200 mm and now 300 mm), high-yield lithography, mature deposition and etch processes, and massive economies of scale that can never be approached by InP fabs.
What silicon photonics cannot do is generate light. As established in Section V-3, silicon has an indirect bandgap and is a poor light emitter. Silicon photonic devices therefore have to be paired with an external laser — usually InP-based — that feeds light into the silicon photonic chip via butt-coupling, grating coupling, or hybrid integration. The combination is sometimes called “InP-on-silicon” or “heterogeneous integration”; the trade-off is that the laser remains the highest-cost and most-constrained component, but everything else can be fabricated at silicon foundry economics.
The device-level building blocks of silicon photonics are mature. Silicon waveguides — narrow strips of crystalline silicon surrounded by silicon dioxide cladding — confine light with low loss at 1310 nm and 1550 nm wavelengths. Silicon-based Mach-Zehnder modulators and ring modulators can encode data onto a CW light beam at 50-100 Gbaud rates. Germanium-on-silicon photodetectors (germanium is also indirect-bandgap but is an adequate detector material because detection efficiency requirements are looser than emission requirements) can convert received light back to electrical signals at the same rates. Wavelength multiplexers and demultiplexers can be fabricated from cascaded ring resonators or arrayed waveguide gratings.
The fabrication step that distinguishes silicon photonics from conventional CMOS is the addition of a process module specifically for the optical devices: a silicon thickness optimization for waveguide confinement, sometimes the deposition of additional cladding materials, the integration of germanium photodetector epitaxy, and the integration of laser dies (which is typically a post-fab packaging step rather than a wafer-level integration). The major silicon foundries that have built silicon photonics process flows are Tower Semiconductor (TSEM), GlobalFoundries (GFS), and TSMC, with each offering somewhat different platforms and process design kit (PDK) libraries.
Why the foundry layer is the leverage point
The dominant investor question in the silicon photonics space is: where does the value capture occur? Is it at the device-design layer (where Marvell, Credo, Broadcom, NVIDIA, and various startups design the silicon photonic chips themselves), the foundry layer (TSEM, GFS, TSMC fabricate them), or the laser layer (LITE, COHR, and the Japanese suppliers provide the unsubstitutable InP light source)?
The historical answer in conventional CMOS is mixed: foundries (TSMC) and fabless design houses (NVIDIA, AMD, Broadcom) both capture substantial value, with the balance favoring the foundry when fabrication is the bottleneck and favoring the design house when innovation is the bottleneck. Silicon photonics has fewer participants on the design side and even fewer participants on the foundry side, which suggests the bargaining dynamics tilt toward whichever layer has less competition.
The foundry layer in silicon photonics is structurally tight. Tower Semiconductor (TSEM) has positioned itself as the merchant silicon photonics foundry, with the 2025 silicon photonics segment revenue at $228 million (up from $106 million in 2024). Tower has been able to extract customer prepayments to fund capacity expansion: $920 million of capex is 70% funded by hyperscaler-customer prepayments, and 70% of forward capacity is reserved through 2028. This is an unusual structure for a foundry — it amounts to take-or-pay financing of capacity from the eventual buyer, and it implies that the buyer perceives the capacity as scarce enough to pre-commit working capital to securing it.
GlobalFoundries (GFS) launched the SCALE silicon photonic platform in May 2026, with management guidance for silicon photonics revenue to roughly double in 2026 (~$400M run rate from a 2025 base of ~$200M, per Q1 2026 earnings commentary — note that the 2026-05-04 press release and the Q1 2026 earnings call are the primary sources, and the data capture process flagged that the $400M number rests on call-Q&A commentary rather than 8-K language). GFS has positioned its silicon photonics offering around CWDM/DWDM architectures and around the emerging Optical Compute Interconnect (OCI) MSA standard for AI scale-up fabrics.
TSMC’s silicon photonics offering is less publicly profiled but appears in multiple AI design wins as the foundry-of-record for NVIDIA’s CPO program. TSMC discloses no segment-level silicon photonics revenue; the exposure shows up in their general advanced packaging revenue and in their HPC platform commentary.
The investor argument for the foundry layer is structural: there are three relevant foundries (TSEM, GFS, TSMC), versus dozens of fabless companies designing silicon photonic devices. The foundries control the production cost curve, the qualification timeline, and the capacity allocation. They are the equivalent of TSMC’s position in the GPU value chain: the layer where the manufacturing bottleneck binds and where the bargaining power concentrates.
The counter-argument is that silicon photonics device design is more differentiated than logic chip design. A silicon photonic modulator’s performance — particularly its modulation efficiency at high bit rates and its insertion loss — depends on subtle physics that has not commoditized in the way that digital logic has. Companies that develop genuinely better modulator designs (Ayar Labs, Lightmatter, DustPhotonics pre-acquisition) can extract value at the design layer rather than ceding it to the foundry. This is why Credo’s acquisition of DustPhotonics for $750M cash plus earnouts (totaling up to $1.3B with the share component) is structurally meaningful — they are buying the design IP rather than the foundry capacity, which suggests they see device-level differentiation as the value capture point.
The balanced read: both the foundry layer and the device-design layer will capture meaningful value through the silicon photonics ramp. The foundry layer is more capital-intensive and has higher barriers to entry but lower potential margin per unit shipped; the device-design layer is lower-capital but has higher competitive entry and faster obsolescence cycles. An investor portfolio that includes Tower Semiconductor (foundry pure-play), Credo (device + system integration), and Marvell (vertically integrated device + system) captures multiple layers of the silicon photonics stack with imperfect but real exposure.
Wafer-scale economics
The economic argument for silicon photonics rests on wafer-scale fabrication. An InP fab today operates on 3-inch or 4-inch wafers (75 mm or 100 mm diameter); a silicon foundry operates on 200 mm or 300 mm wafers. The wafer area difference is roughly 16x (going from 75 mm to 300 mm). Combined with the higher yields, more advanced lithography, and amortized capex of a silicon foundry, the cost per square millimeter of fabricated device falls by an order of magnitude when the same device is fabricated in silicon rather than InP.
For pluggable optics, this hasn’t mattered much because the per-module bill of materials is dominated by the optical sub-assembly mechanical complexity, not the chip cost. For CPO modules, where the per-port optical engine is a much smaller mechanical structure but a larger chip footprint, the wafer-scale economics start to matter materially. Silicon photonic engines fabricated at 300 mm with high yields could produce CPO modules at a cost per port substantially below what discrete InP-based assemblies can achieve at scale.
The transition path matters for the laser-supply math. As silicon photonics fabrication grows, the InP demand per port shifts from “an entire transceiver’s worth of modulators and detectors” to “just the laser.” This is what enables the CPO 0.25-lasers-per-lane architecture: silicon photonic modulators replace the per-lane InP modulators, leaving the laser as the only InP-fabricated component. The wafer-scale economics of silicon then drive down the per-port total cost even as the laser-cost share rises.
Marriage with InP lasers: heterogeneous integration approaches
The mechanical question of how to get light from an InP laser into a silicon photonic chip has been engineered in three distinct ways, each with trade-offs.
First, butt-coupling: the InP laser die is aligned edge-to-edge with the silicon waveguide, and light is launched directly across the interface. This is simple but requires sub-micron mechanical alignment, which is expensive in volume production. Insertion losses are 1-3 dB depending on alignment quality.
Second, grating coupling: light from the InP laser is launched vertically into the silicon photonic chip via a diffraction grating that converts the vertical beam into a horizontal in-plane mode in the silicon waveguide. This relaxes the mechanical tolerance significantly — alignment becomes a 5-10 micron problem rather than a sub-micron problem — but at the cost of higher insertion loss (3-5 dB) and wavelength-dependent coupling efficiency.
Third, hybrid integration via die bonding: the InP laser die is bonded directly onto the silicon photonic chip, either flip-chip or epi-side-down, with the active region positioned to launch light into the silicon waveguide through a transition structure. This is the lowest-loss approach (sub-1 dB) but the highest-complexity manufacturing step.
POET Technologies has built its product strategy around a proprietary optical interposer that purports to enable wafer-scale passive alignment of laser dies, modulator dies, and electronic dies onto a common dielectric waveguide layer. The technical claim is that the interposer’s tight optical mode confinement combined with photolithographically-defined alignment features allows laser-to-waveguide coupling without active alignment. If the claim holds at production volumes, it could reduce CPO module assembly cost meaningfully. The investor concern is that POET has not yet demonstrated production volume — Section V-6 addresses this in detail.
Acronyms used in this section
• SOI — Silicon-on-Insulator; the wafer technology used for silicon photonics.
• PDK — Process Design Kit; the design library a foundry provides to its customers.
• MSA — Multi-Source Agreement.
• OCI — Optical Compute Interconnect; an emerging MSA for AI scale-up fabrics.
• PIC — Photonic Integrated Circuit.
V-6. US-listed optical investment expressions
The twelve US-listed names with material optical exposure are each analyzed below. The structure is consistent across names: business description, AI-segment revenue and percentage of consolidated, customer concentration, current valuation context, key product line, execution-likelihood scoring, and counter-case. A two-level Total Addressable Market (TAM) frame — layer-level (what the broader segment generates in revenue) and company-product-level (what the named name can plausibly capture) — is provided where the data allows. All consensus and price data referenced is as of 2026-05-12.
Also, please note: These are not my usual “Dossier” Deep Dives. I made this research because I wanted to discover the breadth and width of the various players. Expect more deep research on many of these companies in the next few weeks as I keep diving more, trying to decide where to allocate my own capital.
